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T DU C E NT PRO LACEM r at (R) TE ente O LE R EP OBS ENDED upport C om/tsc rsil.c OMM h cal S REC rData ni ww.inte ec Sheet NO January 1996, Rev B u T L or w I act o cont -INTERS 8 1-88
EL4393
FN7165
Triple 80MHz Video Amplifier w/Disable
The EL4393 is three wideband currentfeedback amplifiers optimized for video performance. Each amplifier can drive a load of 150 at video levels. Each amplifier has a disable capability, which is controlled by a TTL/CMOS compatible logic signal. The EL4393 operates on supplies as low as 4V up to 15V. Being a current-feedback design, the bandwidth stays relatively constant at approximately 80MHz over the 1 to 10 gain range. The EL4393 has been optimized for use with 1300 feedback resistors at a gain of 2. When the outputs are disabled, the supply current consumption drops, by about 4mA per channel that is disabled. This feature can be used to reduce power dissipation.
Features
* 80MHz -3dB bandwidth for gains of 1 to 10 * 900V/s slew rate * 10MHz bandwidth flat to 0.1dB * Excellent differential gain and phase * TTL/CMOS compatible * Available in SOL-16
Applications
* RGB drivers * RGB multiplexers * RGB gain blocks
Pinout
EL4393 (16-PIN PDIP, SO) TOP VIEW
* Video gain blocks * Coax cable driver * ADC drivers/input multiplexer
Ordering Information
PART NUMBER EL4393CN EL4393CM TEMP. RANGE -40C to +85C -40C to +85C PACKAGE 16-Pin PDIP 16-Pin SOL PKG. NO. MDP0031 MDP0027
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL4393
Absolute Maximum Ratings (TA = 25C)
Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . .+33V Voltage at VS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Voltage at VS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V Voltage between VIN+ and VIN-. . . . . . . . . . . . . . . . . . . . . . . . . .6V Current into VIN+ or VIN- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Open-Loop DC Electrical Specifications
PARAMETER VOS TCVOS IB+ IBTCIBCMRR -ICMR PSRR -IPSR ROL RIN VIN VO ISC IO, DIS DIS VIL DIS VIH DIS IIL DIS IIH ICC (en) ICC (dis) IEE (en) IEE (dis) NOTES: Input Offset Voltage Temperature Coefficient of VOS IIN+ Input Bias Current IIN- Input Bias Current Temperature Coefficient of IBCommon-Mode Rejection Ratio (Note 1) IIN- Input Common-Mode Current (Note 1) Power Supply Rejection Ratio (Note 2) IIN- Current Supply Rejection (Note 2) Transimpedance IN+ Input Impedance IN+ Input Range Output Voltage Swing; RL = 1k Short-Circuit Current (Note 3) Output Current when Disabled Disable Voltage for Logic Low Disable Voltage for Logic High Disable Logic Low Input Current Disable Logic High Input Current DESCRIPTION
Supplies at 15V, Load = 1k TEMP +25C Full +25C +25C Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C 15 6 13 4 2.2 3 0 20 11 18 9 25 5 29 16 28 14 13 12 40 100 50 50 MIN TYP 2 50 0.2 10 25 58 3 58 2 217 2 13.5 13 70 5 150 0.8 5 8 5 65 MAX 15 UNITS mV V/C A A nA/C dB A/V dB A/V k M V V mA A V V A A mA mA mA mA
Positive Supply Current all Channels Enabled Positive Supply Current all Channels Disabled Negative Supply Current all Channels Enabled Negative Supply Current all Channels Disabled
1. VCM = 10V for VS = 15V. 2. VOS is measured at VS = 4.5V and VS = 16V, both supplies are changed simultaneously. 3. Only one output short-circuited. Pulse test or use heatsink.
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EL4393
AC Electrical Specifications
PARAMETER SR SR tS BW BW Peaking dG d Slew Rate (Note 2) Slew Rate w/5V Supplies (Note 3) Settling Time to 1% 5VP-P 5V Step (Note 4) Bandwidth, -3dB 5V Supplies, -3dB Bandwidth, -0.1dB 5V Supplies, -0.1dB -3dB BW Tests Differential Gain at 3.58MHz at 5V Supplies (Note 5) Differential Phase at 3.58MHz at 5V Supplies (Note 5) Supplies at 15V, Load = 150 and 15pF, except where noted. Rf1 and Rf2 = 1500; AV = 2, TA = 25C.(Note 1) DESCRIPTION MIN TYP 960 470 32 80 60 16 21 0.6 0.03 0.30 0.088 0.096 MAX UNITS V/s V/s ns MHz MHz MHz MHz dB % % () ()
NOTES: 1. Test fixture was designed to minimize capacitance at the IN+ input. A "good" fixture should have less than 2pF of stray capacitance to ground at this very sensitive pin. See application notes for further details. 2. RL = 300, -5V to +5V swing, SR measured at 20% to 80% 3. -2V to +2V swing, SR measured at 20% to 80%. 4. RL = 300. 5. DC offset from -0.7V through +0.7V AC amplitude is 286mVP-P, equivalent to 40 ire.
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EL4393 Typical Performance Curves
Gain Flatness vs Rf at 5V Gain Flatness vs Rf at 15V
Phase vs Rf at 5V
Phase vs Rf at 15V
Gain of 5, 10 vs Various Rf, Rg at 5V
Gain of 5, 10 vs Rf, Rg at 15V
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EL4393 Typical Performance Curves
(Continued)
Disabled Isolation Test at 5V
Disabled Isolation Test at 15V
Cin--vs Peaking
Voltage Noise
Differential Gain & Phase at 3.58MHz
EL4393 MUX Channel Channel Isolation
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EL4393 Typical Performance Curves
(Continued)
Supply Current vs Supply Voltage
Maximum Power Dissipation vs Ambient Temperature-- 16-Pin PDIP
Maximum Power Dissipation vs Ambient Temperature-- 16-Pin SOL
Small Signal Pulse Response
Large Signal Pulse Response
Small Signal Enable/Disable with +VE Voltage
Enable/Disable with -VE Voltage Output
Typical Application for EL4393, and General Rules for PCB Layout
The figure shows two EL4393s configured as a 2:1 RGB multiplexer, and cable driver, driving 75, back terminated cables. Each channel of the EL4393 is configured to give a gain of two, to make up for the losses of the back terminating resistor. In this example, the Disable pins of each RGB section are driven by a complementary TTL "select" signal. Larger multiplexers can be assembled, with a 1-of-n TTL decoder selecting each RGB triplet.
The circuit gives channel isolations of typically better than -50dB at 10MHz, and with a 20dB/decade slope, extending down to better than -90dB at frequencies below 100kHz. The schematic does not show things like power supply decoupling, or pcb layout, grounding and signal returns, but these will all affect the overall performance of the circuit, and care should be taken with these aspects. It is recommended that the VCC and VEE pins each be decoupled by a 0.1F NPO or X7R dielectric ceramic capacitors to ground within 0.1 inch of the part, and in parallel with the 0.1F, a 47F tantalum capacitor, also to ground. The 47F capacitors should be within 0.25 inch of their power
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EL4393
pins. The ground plane should be underneath the package, but cut away from the In- inputs. Care should be taken with the center channel feedback--it must be kept away from any of the In+ or In- pins, if it has to go under the package. Route the G-out line between the pin 3 ground and the pin 4 In- if going under the package is essential. Otherwise, loop the Gout trace around all the other circuitry, to its Rf resistor. The Rf and if used, Rg resistors should be on the input side of the package, to minimize trace length on the In- pins. The digital input disables are on the output side of the package, so that a good ground plane down the center of the board underneath the package will isolate any fast edges from the sensitive inputs.
TYPICAL APPLICATION CIRCUIT
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EL4393 EL4393 Macromodel
* Revision A, July 1993 * Enhancements include PSRR, CMRR, and Slew Rate Limiting * Connections: +input * | -Input * | | +Vsupply * | | | -Vsupply * | | | | Putput * | | | | | * subckt EL4393/EL 3 2 746 * * Input Stage * e1 10 0 3 0 1.0 vis 10 9 0V h2 9 12 vxx 1.0 r1 2 11 50 l 1 11 12 29 nH iinp 3 0 0.2 A iinm 2 0 10 A * * Slew Rate Limiting * h1 13 0 vis 600 r2 13 14 1K d1 14 0 dclamp d2 0 14 dclamp * * High Frequency Pole * e2 30 0 14 0 0.00166666666 l5 30 17 1.2 H c5 17 0 1 pF r5 17 0 500 * * Transimpedance Stage * g1 0 18 17 0 1.0 rol 18 0 250k cdp 18 0 2.2 pF * * Output Stage * q1 4 18 19 qp q2 7 18 20 qn q3 7 19 21 qn q4 4 20 22 qp r7 21 6 4 r8 22 6 4 ios1 7 19 2.5 mA ios2 20 4 2.5 mA * * Error Terms * ivos 0 23 2 mA vxx 23 0 0V e4 24 0 3 0 1.0 e5 25 0 7 0 1.0 e6 26 0 4 0 1.0 r9 24 23 1K
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EL4393
r10 25 23 1K r11 26 33 1K * * Models * .model qn npn (is=5e-15 bf=100 tf=0.2nS) .model qp pnp (is=5e-15 bf=100 tf=0.2nS) .model dclamp d (is=1e-30 ibv=0.266 bv=1.5 n=4) .ends
SIMPLIFIED SCHEMATIC OF ONE CHANNEL OF EL4393
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